1. Field of the Invention
The present invention relates to a technology for separating a processor that performs process by using data recorded in a cache memory.
2. Description of the Related Art
Typically, a cache memory has been used to solve a problem of data delay occurring between a processor and a main memory. A cache-memory managing device that manages the cache memory maintains coherence between the main memory and the cache memory according to write back algorithm, for example.
In separating the processor by reconfiguring a system including the processor, the cache-memory managing device requests the processor for a separation. Upon receiving a response from the processor, the cache-memory managing device invalidates the cache memory and separates the processor.
According to the write back algorithm, because of its characteristics, when the processor updates the data of the cache memory, the updated data is not simultaneously written back into the main memory. Therefore, in invalidating the cache memory for separating the processor, the cache-memory managing device determines whether the write back of the data accessed by the processor is necessary. When the write back is necessary, the cache-memory managing device writes back the data, and maintains coherence between the main memory and the cache memory.
In recent years, following the improvement of processor performance and the increase in the memory capacity of the cache memory, the cache memory is, in some cases, shared by a plurality of processors. In a system with a plurality of processors mounted thereon, there are many cases where an arbitrary processor needs to be dynamically separated to reconfigure the system. However, according to the conventional technology, a processor separation process becomes complex, and the processor cannot be separated quickly.
That is, even in the system in which a plurality of processors shares a cache memory, it is quite important to separate a processor safely and promptly from the system, thereby increasing system availability.